Image sensors are used in a variety of different types of digital image capture systems, including products such as scanners, copiers, and digital cameras. The image sensor is typically composed of an array of light-sensitive pixels that are electrically responsive to incident light reflected from an object or scene whose image is to be captured.
The performance of an image capture system depends in large part on the sensitivity of each individual pixel in the sensor array and its immunity from noise. Pixel sensitivity is defined here as being related to the ratio of a change in the pixel output voltage to the photogenerated charge in the pixel. Noise can be caused by a variety of known sources. An image sensor with increased noise immunity yields sharper, more accurate images in the presence of environmental and other noise.
Improving the sensitivity of each pixel permits a reduction in exposure time which in turn allows the capture of images at a greater rate. This allows the image capture system to capture motion in the scene. In addition, higher pixel sensitivity also helps to capture acceptable quality images under low light conditions.
One way to increase pixel sensitivity is to increase the efficiency of the photodiode by changing the photodiode response characteristics. Doing so, however, can require deviating from a standard CMOS integrated circuit fabrication process, thereby further increasing the cost of manufacturing the image sensor circuit.
The individual pixels of a CMOS imager sensor array typically contain a photodiode or phototransistor as a light detecting element. Photogenerated charges are collected in accordance with the intensity of light illuminating the photodiode or phototransistor. An analog signal is generated from the collected charges having a magnitude approximately proportional to the intensity of light illuminating the light detecting element.
With reference to FIG. 1, a portion of a conventional pixel sensor array is depicted. The pixel sensor array contains a plurality of pixels 100 where each pixel 100 contains a reset transistor 102, a first terminal of which is coupled to a source voltage terminal (e.g., Vdd), a second terminal of which is coupled to a photodiode 104. The second terminal of reset transistor 102 is also coupled to a gate of source-follower  transistor 108. A first source/drain terminal of s is also coupled to the source voltage terminal (e.g., Vdd). A second source/drain terminal of source-follower transistor 108 is coupled to a row select transistor 106.
Row select transistor 106 is coupled to the column bus 132, which is coupled to a dual-stage sample and hold (SH) circuit. A first SH circuit (SHR) consists of a first SH transistor 120. SH transistor 120 is also coupled to a first storage capacitor 122 and also coupled to column select switch 148. Switch 148 is also coupled to an input of differential amplifier 135.
A second SH circuit (SHS) consists of a second SH transistor 128. SH transistor 128 is also coupled to a second storage capacitor 130 and also coupled to column select switch 152. Switch 152 is also coupled to an input of differential amplifier 135. The output of differential amplifier 135 provides the difference between the reset voltage (VRST) and the integration, or signal voltage VSIG.
During operation, the photodiode 104 is reset by activating reset transistor 102, thereby resetting the charge collection node of the photodiode 104 to the source voltage (e.g., Vdd). The reset transistor 102 is then deactivated and the photodiode 104 is then exposed to incident light during an integration period. During the integration period, the photodiode discharges the reset voltage in proportion to the intensity of the incident light.
The row select transistor 106 is then activated and the photodiode signal VSIG is transferred to the column bus 132 and to the second SH circuit (SHS) where the charge is stored on storage capacitor 130.
The photodiode 104 is reset again and the reset voltage level VRST stored by the photodiode 104 is then transferred to the first SH circuit and stored in storage capacitor 122.
Thereafter, the two respective values stored by capacitors 122 and 130, namely, a reset voltage VRST and a signal voltage VSIG, are subtracted and the difference between the two voltage levels indicates the level of exposure of the photodiode 104 to the incident light.
Some limitations on the above-described double sampling process do exist, however. For instance, the measurement of the amount of light detected by the photodiode 104 is limited due to noise that is generated by the switching of the reset transistor 102. That noise, “kTC noise,” where k is Boltzmann's constant, T is temperature in degrees Kelvin, and C is the size of the intrinsic capacitance of the photodiode 104 in Farads, is fundamentally present whenever a capacitor is set to a voltage due to fluctuations in the number of electrons present in the capacitor's “sea of electrons.”
One way to suppress kTC noise is to perform correlated double sampling (CDS) on the pixel. CDS is similar to the process described above except that the sample of the pixel reset voltage and the sample of the integration voltage are taken from the same frame.
During operation, the photodiode 104 is reset by activating reset transistor 102, thereby resetting the charge collection node of photodiode 104 to the source voltage (e.g., Vdd). The reset voltage is then sampled and stored. The reset transistor 102 is then activated again to reset the photodiode 104 and the photodiode 104 is then exposed to incident light during an integration period. During the integration period, the photodiode discharges the reset voltage in proportion to the intensity of the incident light. The resulting integration or signal voltage is then sampled and stored. Thereafter, the reset voltage and signal voltage are subtracted in order to determine the magnitude of light exposure of the photodiode during integration.
While CDS is known in the art to reduce kTC noise in CMOS imagers, CDS is typically performed sequentially for each pixel on a column by a common pair of sample and hold (SH) circuits, such as SHR and SHS of FIG. 1.
More recently, efforts have been made to perform CDS, and thereby reduce kTC noise, with circuitry located within each individual pixel, rather than on the column line. The process is described in a paper by R. Morrill, entitled “Intra-Pixel Reset Noise Cancellations,” distributed at the 2001 IEEE Workshop on Charge Coupled Devices and Advanced Image Sensors, Jun. 7-9, 2001, Lake Tahoe, Nev., the contents of which are incorporated herein by reference.
With reference to the Morrill paper, one of the major drawbacks is that an inordinate amount of power is consumed within the pixel in performing CDS. For example, the power dissipation required to maintain the bias voltage on N4 (in FIG. 1 of the Morrill paper) is excessive. Thus, it is desirable to reduce kTC noise generated within a pixel circuit without consuming excessive power.